verilog - How to use structural unit? -

i write verilog code using simple adder(inbiult in xilinx itself) want replace using rns adder code made , gives module rns(clk,rst,a,b,c) a,b input of rns adder , c output.

and code using simple adder given below.in code using enable ,for have use block....but in structural modelling(when call rns adder) how deal enable?

module output_adder_8(enable,s089,s318,s175,s250,s289,s118,s075,s350,s189,s218,s375,s050,s389,s018,s275,s150,r1,r3,r5,r7); input enable; input [13:0] s089,s175,s250,s318,s289,s118,s075,s350,s189,s218,s375,s050,s389,s018,s275,s150; output reg[15:0] r1,r3,r5,r7; reg [11:0] c,d,e,f,g,h,i,j; //reg [3:0] countp=4'b0000;  always@* begin  if (enable)   c<= s089+s318;  d<= s175+s250;  r1<= c+d;  e<= s289+s118;  f<= s075-s350;  r3<=f-e;  g<= s218-s189;  h<= s375+s050;  r5<=g+h;  i<= s018-s389;  j<= s275-s150;  r7<=i+j;   end endmodule     module shift_adder_8a( clk, z0, s018, s050, s075, s089,enable0 );   input clk;  input [12:0] z0;  output reg [13:0] s018;  output reg [13:0] s050;  output reg [13:0] s075;  output reg [13:0] s089;  output reg enable0;   // temp reg declaration reg [3:0] count0=4'b0000; reg [13:0] d01,            d02,               d03,                 d04,               d05,               e01,               e02,               e03,               e04;  @(posedge clk )  begin        d01 <= z0<< 3;       d02 <= z0 << 4;       d03 <= z0 << 6;          if (count0==4'b0110)         d04 <= e01 << 1;         d05 <= e02 << 1;                 e01 <= d01 + z0;          e02 <= d02 + e01;        e03 <= d03 + e02;                 e04 <= e02 + d05;         s018 <= d04;         s050 <= d05;         s075 <= e04;         s089 <= e03;         enable0<=1'b1;      end 

if want use own adder design instead of whatever builtin or equivalent synthesis+compliler tool gives you, need instantiate module instead of use + operator. retain enable line, can have separate combinational block (either always @* or assign) passes output through if enable on or 0s on output if enable off. heres example:

module( enable, clk, rst, a, b, c );   input clk;   input rst;   input enable;   input [15:0] a;   input [15:0] b;   output [15:0] c;    wire [15:0] adder_out    // adder   rns rns_adder( .clk(clk), .rst(rst), .a(a), .b(b), .c(adder_out) );    // enable line   assign c = (enable) ? adder_out : 16'b0;  endmodule 

note: don't use non-blocking assignment (<=) in always @* blocks, use blocking assignment (=)