verilog - Synopsys Design Compiler and PrimeTime timing analysis report remain same -

i had done timing analysis of counter in both synopsys design compiler , primetime, got same output! problem ?

then how primetime timing analysis become more accurate dc?

design file used counter.v , given below.

module counter ( out, clk, reset ) ;     input        clk, reset;    output [3:0] out;     reg [3:0]    out;     wire [3:0]   next;     // statement implements reset , increment    assign       next = reset ? 4'b0 : (out + 4'b1);     // implements flip-flops    @ ( posedge clk ) begin       out <= #1 next;    end   endmodule // counter 

design compiler output generated giving input counter.v , , clock period of 2.the design compiler output shown below.

write_sdf ${name}.sdf information: annotated 'cell' delays assumed include load delay. (uid-282) information: writing timing information file '/home/student/labs/jithin_prjct/jith/count.sdf'. (wt-3) information: updating design information... (uid-85) 1 create_clock clk -period 2 1 report_timing information: updating graph... (uid-83) information: updating design information... (uid-85)  **************************************** report : timing         -path full         -delay max         -max_paths 1 design : count version: e-2010.12-sp2 date   : fri mar 20 22:08:55 2015 ****************************************  operating conditions: typical   library: saed90nm_typ wire load model mode: enclosed    startpoint: out_reg[0] (rising edge-triggered flip-flop clocked clk)   endpoint: out_reg[3] (rising edge-triggered flip-flop clocked clk)   path group: clk   path type: max    des/clust/port     wire load model       library   ------------------------------------------------   count              forqa                 saed90nm_typ    point                                    incr       path   -----------------------------------------------------------   clock clk (rise edge)                    0.00       0.00   clock network delay (ideal)              0.00       0.00   out_reg[0]/clk (dffx1)                   0.00       0.00 r   out_reg[0]/q (dffx1)                     0.18       0.18 f   u25/qn (nor2x0)                          0.11       0.29 r   u21/q (ao21x1)                           0.12       0.41 r   u15/q (ao21x1)                           0.10       0.51 r   u14/q (mux21x1)                          0.12       0.63 r   out_reg[3]/d (dffx1)                     0.04       0.67 r   data arrival time                                   0.67    clock clk (rise edge)                    2.00       2.00   clock network delay (ideal)              0.00       2.00   out_reg[3]/clk (dffx1)                   0.00       2.00 r   library setup time                      -0.07       1.93   data required time                                  1.93   -----------------------------------------------------------   data required time                                  1.93   data arrival time                                  -0.67   -----------------------------------------------------------   slack (met)                                         1.26 

primetime output generated giving input netlist file of counter , sdf file of counter (both generated design compiler) , clock period of 2. primetime output shown below.

report_timing **************************************** report : timing     -path_type full     -delay_type max     -max_paths 1 design : count version: e-2010.12-sp1 date   : fri mar 20 22:08:14 2015 ****************************************     startpoint: out_reg[0] (rising edge-triggered flip-flop clocked clk)   endpoint: out_reg[3] (rising edge-triggered flip-flop clocked clk)   path group: clk   path type: max    point                                    incr       path   ---------------------------------------------------------------   clock clk (rise edge)                    0.00       0.00   clock network delay (ideal)              0.00       0.00   out_reg[0]/clk (dffx1)                   0.00       0.00 r   out_reg[0]/q (dffx1)                     0.18 *     0.18 f   u25/qn (nor2x0)                          0.11 *     0.29 r   u21/q (ao21x1)                           0.12 *     0.41 r   u15/q (ao21x1)                           0.10 *     0.51 r   u14/q (mux21x1)                          0.12 *     0.63 r   out_reg[3]/d (dffx1)                     0.04 *     0.67 r   data arrival time                                   0.67    clock clk (rise edge)                    2.00       2.00   clock network delay (ideal)              0.00       2.00   out_reg[3]/clk (dffx1)                              2.00 r   library setup time                      -0.07 *     1.93   data required time                                  1.93   ---------------------------------------------------------------   data required time                                  1.93   data arrival time                                  -0.67   ---------------------------------------------------------------   slack (met)                                         1.26 

you different results when analysis performed on post-layout netlist. pre-layout netlist, you're feeding tool same data .lib files perform timing analysis, either in design compiler or primetime. post-layout netlist includes clock tree synthesis, , that's when use primetime. furthermore, notice can analyse setup requirements, , no hold requirements while in pre-layout netlist.